• Must be a US Citizen or Green Card Holder
• Offer contingent on ability to successfully pass a background check and drug screen
Position requires the following skill set:
1. Experience with complex and large-scale FPGA development.
2. Experience with the latest industry FPGA verification methodologies utilizing UVM and SystemVerilog performed on Mentor Questa sim environment.
3. Experience in all aspects of design verification:
a. Verification planning (Verification plan & Verification matrix)
b. Verification testbench development (block-level & system-level)
c. Test case writing
d. Coverage closure (Functional & code-coverage)
i. Simulation (Mentor Questa)
ii. Continuous integration (Bamboo)
iii. Configuration management (git)
iv. Bug-tracking (JIRA)
v. Formal verification ()
4. Excellent oral/written communication and presentation skills.
5. Ability to work effectively in a team.
Experienced debugging/identifying RTL issues